Surachoke ThanapithakChutham SawigunMahidol UniversityMahanakorn University of Technology2019-08-232019-08-232018-04-26Proceedings - IEEE International Symposium on Circuits and Systems. Vol.2018-May, (2018)027143102-s2.0-85057073385https://repository.li.mahidol.ac.th/handle/123456789/45808© 2018 IEEE. In the design of a transistorized filter comprising CMOS devices in a standard technology, the bulk effect possibly introduces resistive loss to the circuit. Compensating for this loss thereby enhancing the filter's passband gain, a negative resistance circuit is usually employed. This paper tackles this issue by introducing novel single-branch biquadratic sections that can be combined to form a 4th-order lowpass filter with automatic loss compensation. The proposed lowpass filter dedicated for biomedical applications that emphasize on power and area minimization. Therefore, all MOSFETs used are biased in the subthreshold region. Fabricated in a 0.35 μm CMOS technology, the prototype chip occupies an area of 0.027 mm2. Operating at a 1.5 V supply, the filter consumes 5.2 nW and provides a cutoff frequency of 100 Hz. The measured -40 dB THD is associated with an input voltage of 60 mVp, while the measured input-referred noise equals 43.9 μVrms. This results in a dynamic range of 59.7 dB. Compared with the state-of-the-art nanopower LPF design, a twofold figure of merit improvement is achieved.Mahidol UniversityEngineeringConference PaperSCOPUS10.1109/ISCAS.2018.8351016