Surachoke ThanapitakChutham SawigunMahidol UniversityMahanakorn University of Technology2019-08-232019-08-232018-09-01IEEE Transactions on Circuits and Systems I: Regular Papers. Vol.65, No.9 (2018), 2774-2783154983282-s2.0-85043456545https://repository.li.mahidol.ac.th/handle/123456789/45792© 2004-2012 IEEE. This paper develops a compact power-efficient CMOS buffer to operate as a nanopower lowpass biquadratic cell. Unlike other recently reported CMOS biquads with passband gains that are attenuated by the bulk effect, this biquad attains a near 0-dB passband gain without gain compensation. It acquires the same levels of input and output common-mode voltages making it useful for cascade realization of a higher order lowpass filter. To demonstrate the potential application of the proposed biquad, a fourth-order lowpass filter was designed based on the proposed biquad circuit and fabricated in the 0.35- CMOS process to serve electrocardiography readout systems. Measurement results show that the filter consumes 4.26-nW static power from a 0.9-V supply providing a 100-Hz cutoff frequency. The prototype chip occupies a silicon area of 0.11 mm2 and contributes an input-referred noise of 80.5. For a 60-Hz input frequency associated with -50-dB third-order harmonic distortion, a dynamic range of 48.2 dB is achieved. The lowest power supply rejection ratio of 40 dB was obtained at 100 Hz. Compared with the previous state-of-the-art designs in the category of nanopower filters, the proposed filter consumes the least power from the lowest supply voltage.Mahidol UniversityEngineeringArticleSCOPUS10.1109/TCSI.2018.2808361