A Chopper Biopotential Instrumentation Amplifier with DSL-Embedded Input Stage Achieving 109 dB CMRR and 400 mV DC Offset Tolerance

Abstract

This paper presents a bio-potential chopper current-balanced instrumentation amplifier (CBIA) that uses a dc-isolated, source-coupled-pair input stage with embedded dc-servo loops. Despite chopping a large electrode offset, gate-source voltage of each input transistor does not vary excessively. As a result, for typical bio-potential input voltages, less than 1 percent THD can be achieved. Hence, excessive power consumption dedicated for linearization of the input stage is no longer needed. This results in 90 % power reduction compared with the most recent CBIA. Fabricated in a 0.35-micron CMOS, the proposed CBIA maintained CMRR over 80 dB up to 0.3 V input offset (109 dB for zero offset). The chip occupies 0.41 sq. mm and consumes 1.19 microwatt from a 3 V supply. The input noise density, input impedance and noise efficiency factor of 91 nV per square-root-hertz, 469 Megaohms at 5 Hz and 2.22 NEF are obtained, respectively. Compared with other recent state-of-the-art CBIAs, this proposed IA attains the lowest NEF and PEF.