A Phase Lead-Lag Synchronous Reference Frame Phase-locked loop for Grid Synchronization of a Single-Phase Inverter
Issued Date
2022-02-18
Resource Type
ISSN
16859545
Scopus ID
2-s2.0-85125091045
Journal Title
ECTI Transactions on Electrical Engineering, Electronics, and Communications
Volume
20
Issue
1
Start Page
123
End Page
132
Rights Holder(s)
SCOPUS
Bibliographic Citation
ECTI Transactions on Electrical Engineering, Electronics, and Communications Vol.20 No.1 (2022) , 123-132
Suggested Citation
Jeraputra C., Pongpaiboon J., Singhavilai T., Tiptipakorn S. A Phase Lead-Lag Synchronous Reference Frame Phase-locked loop for Grid Synchronization of a Single-Phase Inverter. ECTI Transactions on Electrical Engineering, Electronics, and Communications Vol.20 No.1 (2022) , 123-132. 132. doi:10.37936/ecti-eec.2022201.246117 Retrieved from: https://repository.li.mahidol.ac.th/handle/20.500.14594/84289
Title
A Phase Lead-Lag Synchronous Reference Frame Phase-locked loop for Grid Synchronization of a Single-Phase Inverter
Author's Affiliation
Other Contributor(s)
Abstract
In this study, a phase lead-lag synchronous reference frame phase-locked loop (SRF-PLL) is proposed for the grid connection of a single-phase inverter. A tuned filter is employed to enable the phase of the input voltage to be advanced or delayed by ±45 degrees with respect to the grid voltage. The generated orthogonal signals are fed into Park’s transformation. Only the quadrature-phase signal is regulated to zero using a PI controller. Its output determines the estimated frequency. The phase angle is obtained by integrating the estimated frequency. The linearized model of the proposed SRF-PLL is developed and stability analysis is discussed. The viability of the proposed method is tested under computer simulation using MATLAB/Simulink. The method is then implemented on a 32-bit microcontroller and tested with a programmable AC source. The results positively confirm the effectiveness of the method.