Publication: A 1 GHz CMOS analog equalizer for perpendicular magnetic recording
Issued Date
2010-12-01
Resource Type
Other identifier(s)
2-s2.0-79951639183
Rights
Mahidol University
Rights Holder(s)
SCOPUS
Bibliographic Citation
IEEE Region 10 Annual International Conference, Proceedings/TENCON. (2010), 1521-1524
Suggested Citation
Sukarasut Meksiri, Kasin Vichienchom, Decha Wilairat A 1 GHz CMOS analog equalizer for perpendicular magnetic recording. IEEE Region 10 Annual International Conference, Proceedings/TENCON. (2010), 1521-1524. doi:10.1109/TENCON.2010.5686144 Retrieved from: https://repository.li.mahidol.ac.th/handle/20.500.14594/28983
Research Projects
Organizational Units
Authors
Journal Issue
Thesis
Title
A 1 GHz CMOS analog equalizer for perpendicular magnetic recording
Author(s)
Other Contributor(s)
Abstract
This paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW. ©2010 IEEE.