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A 1 GHz CMOS analog equalizer for perpendicular magnetic recording

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dc.contributor.authorSukarasut Meksirien_US
dc.contributor.authorKasin Vichienchomen_US
dc.contributor.authorDecha Wilairaten_US
dc.contributor.otherKing Mongkut's Institute of Technology Ladkrabangen_US
dc.contributor.otherMahidol Universityen_US
dc.date.accessioned2018-09-24T08:56:31Z
dc.date.available2018-09-24T08:56:31Z
dc.date.issued2010-12-01en_US
dc.description.abstractThis paper describes the design of a CMOS analog discrete-time equalizer for perpendicular magnetic recording (PMR) read channel. In this design the structure of analog FIR filter that places rotating switch matrix between DAC and multiplier has been proposed. It reduces an accumulative switching error in analog samples due to rotating switch matrix. A 7-tap filter circuit based on GPR2 target was designed and simulated using TSMC 0.18 μm CMOS process parameters. Simulation results show good agreement with the results of the system level simulation. At 1 GHz sampling frequency the equalizer dissipates 1.5 mW. ©2010 IEEE.en_US
dc.identifier.citationIEEE Region 10 Annual International Conference, Proceedings/TENCON. (2010), 1521-1524en_US
dc.identifier.doi10.1109/TENCON.2010.5686144en_US
dc.identifier.other2-s2.0-79951639183en_US
dc.identifier.urihttps://repository.li.mahidol.ac.th/handle/20.500.14594/28983
dc.rightsMahidol Universityen_US
dc.rights.holderSCOPUSen_US
dc.source.urihttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79951639183&origin=inwarden_US
dc.subjectComputer Scienceen_US
dc.subjectEngineeringen_US
dc.titleA 1 GHz CMOS analog equalizer for perpendicular magnetic recordingen_US
dc.typeConference Paperen_US
dspace.entity.typePublication
mu.datasource.scopushttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79951639183&origin=inwarden_US

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